1. Field of the Invention
The present invention is generally related to the field of memory management in a computer system, and, more particularly, to a method and apparatus for controlling a translation lookaside buffer.
2. Description of the Related Art
Modem computer systems commonly use virtual storage as an effective memory management technique in a multitasking environment. That is, instructions and data references to memory produced by a program within a central processing unit (CPU) are isolated from physical memory using mapping procedures, such as segmentation and/or paging. To translate a virtual address to a physical address with paging, for example, the virtual address is separated into a frame number and an offset, and a lookup in a page table translates, or maps, the virtual memory reference into a physical memory location consisting of a corresponding page number and the same offset. Generally, every memory reference in a fetch-execute cycle goes through this translation process.
One advantage of virtual storage for memory management arises out of the separation of logical and physical memory. That is, the logical and physical memory does not have to be the same size. The size of the logical memory is established by the number of bits in the address space of an instruction word. The size of the physical memory is theoretically determined by the size of the memory address register and the size of the page number and offset in the page table. Practically, however, it is determined by the amount of installed memory. Accordingly, the virtual memory can be substantially larger than the physical memory.
One significant disadvantage of virtual storage is that it slows the overall operation of the computer system. First, every memory access is subject to the translation process, adding significant time to each memory access. Moreover, the page table can be relatively large, and, thus, is normally stored in a relatively slow hard disk drive. Thus, the time required to perform each memory access is compounded by adding an additional access to the relatively slow hard disk drive.
To regain some of the speed lost to the translation process, a small, relatively expensive, high-speed buffer stores a subset of the page table translations. These buffers are commonly referred to as translation lookaside buffers, and they maintain the most recent translations. The TLB is generally effective at substantially reducing the amount of time consumed by the translation process when the translation for the current memory access is stored in the TLB.
In modem CPUs, the operation of the TLB may be less than ideal. Commonly, these CPUs prefetch a plurality of instructions and prepare them for execution in advance. Owing to branches in a program, it is possible that the prefetched instructions will not be used if the branch is incorrectly predicted. Accordingly, the CPU includes a provision for flushing the incorrectly prefetched instructions and resetting the status of the CPU to its proper state at the time that the incorrectly predicted branch was taken. The prepatory work done on the prefetched instructions is not commited to the state of the CPU until time for execution so as to minimize the resetting operation. For example, instructions and data references to memory may require the page table and the translation lookaside buffer to be updated. However, the CPU does not allow the speculative updates to be committed to the page table or the translation lookaside buffer, effectively stalling the prefetch operations.
The present invention is directed to a method of solving, or at least reducing the effects of, some or all of the aforementioned problems.
In one aspect of the present invention, a method is provided for controlling a translation lookaside buffer. The method is comprised of receiving a virtual memory address, and initiating a table walk process to convert the virtual memory address to a physical address. A physical address generated by the table walk process is examined to determine if a conflict with a physical address of a pending memory access request exists. The table walk process is cancelled in response to determining that the conflict exists.
In another aspect of the instant invention, an apparatus for controlling a translation lookaside buffer is provided. The apparatus comprises a translation unit, a buffer, and a comparator. The translation unit is adapted to initiate a table walk process to convert a virtual memory address to a physical address. The buffer is adapted to store pending memory access requests previously processed by the translation unit. The comparator is adapted to determine if a physical address generated by the table walk process of the translation unit conflicts with a physical address of at least one of the pending memory access requests, and deliver a control signal to the translation unit for canceling the table walk process in response to determining that a conflict exists.